The invention relates to a pulse generating circuit for microcomputers, and more particularly to a pulse generating circuit in which a time base clock and an event base clock are made to realize its synchronous operation.
One of various fundamental types of configurations of pulse generating circuits is a pulse generating circuit in which a time or the number of occurrences of events is counted by counters or timers to realize a synchronized pulse generating operation. Generally, timers or counters are used for implementation of the synchronous operation of the pulse generating circuit. The pulse generating circuit includes timers, compare registers and a flip-flop circuit. Previous to the counting of time or the number of occurrences of events, predetermined count values about both time and the number of occurrences of events are set or stored in the compare resisters, after which the timer initiates the count up of times or events. When the count value of the timer corresponds to the predetermined values set in the compare register, the compare register generates and subsequently delivers a correspondence signal which means the correspondence between the current count value in the time count or the event count and the predetermined count value set in the compare register. When the correspondence between the current count value and the predetermined count value is confirmed, the flip-flop is activated for a generation and a subsequent delivery of the pulse signal.
As described the above, there exit two types of count, and thus one is the count of times and the other is the count of the number of occurrences of events. Needless to say, both the above counts by the timer or counter, and thus the time counts and the event counts are available to realize the synchronous pulse generating operation. In the prior arts, the timers or the counters are basically required for the time count and the event counts respectively. Namely, it is necessary to use both a timer for the time count and a timer for the event count. If a single timer or a counter is used, it is necessary to select the time count mode or and the event count mode prior to the initiation of the counting operation. However, if the time count and the event count are hybridized in the count operation for a single pulse output, at least two timers or counters are used. A typical conventional configuration of the pulse generating circuit will be described with reference to FIGS. 1 and 2.
The conventional pulse generating circuit includes first and second timers 1 and 13, first and second compare registers 10 and 11, a capture register 12 and a SR flip-flop circuit 6. The first timer 1 conducts the event count and the first compare register 10 compares the values about the event counts. The second timer 13 conducts the time count and the second compare register 11 compares the values about the time counts. A reference signal INTP on a line 2 causes the first timer 1 to RESET, and thus to be cleared for a subsequent initiation of the event count operation. The first timer 1 fetches an external event signal TI as a clock signal on a line 4 for a count of the number of the occurrences of events. Since the event count and the time count are exclusive, during the event count operation, the time base count operation is not useful. During the event counts, a 0 signal occurs on the S (SET) input line of the flip-flop 6 and a 1 signal occurs on the R (RESET) input line of the flip-flop 6 thereby the flip-flop takes the RESET state or the 0 state and thus a 1 state of the pulse signal TO occurs the output line 7 of the flip-flop 6. A predetermined value about the event count is set or stored in the first compare register 10. The compare register 10 fetches the current count value of the number of the external event occurrences from the first timer 1 for a subsequent comparison of the current count value with the predetermined value set or stored therein. The count up operation of the event occurrences is continued until the present count up value reaches the predetermined value set in the compare register 10. If the correspondence between the current count value of the number of the external event occurrences and the predetermined value set or stored in the compare register 10 is confirmed, the compare register 10 generates a correspondence signal 5 which means the correspondence between the current count value and the predetermined value. When the correspondence signal occurs at the first compare register 10, the count up operation of the even occurrences is completed.
Such correspondence signal 5 is further transmitted as an interrupt signal to an interrupt controller which is not illustrated. The interrupt controller receives various interrupt for a subsequent control thereof according to those priorities. After that the interrupt controller provides a controlled interrupt to a CPU (central processing unit) which is not illustrated. During the interrupt processing, the CPU fetches the counting value stored in the capture register 12 for addition of the fetched counting value and a predetermined value. A value provided by the addition between the fetched counting value and the predetermined value is stored in the second compare register 12.
The occurrence of the correspondence signal 5 also provides a timing of the capture to the capture register 12. The capture register 12 captures the present count up value from the second timer 13.
The occurrence of the correspondence signal 5 also the flip-flop 6 activates. Thus, a 1 signal occurs on the S input line of the flip-flop 6 and a 0 signal occurs on the R input signal line of the flip-flop 6 thereby the output signal TO occurring on the output line 7 of the flip-flop 6 takes the 1 state so that the flip-flop 6 takes the SET state. Following the completion of the counting up operation of the event occurrences by the first timer 1, the second timer initiates a count up operation of times. The second timer 13 fetches time signals which occurs on a line 3 as clock signals for a count up operation about the time. The count up operation of the time is continued until the correspondence between the present count value of the time and the predetermined value set in the compare register 11 appears. During the count up of the time, the flip-flop 6 remains at the SET state or the activated state. When the correspondence between the present count up value of the second timer 13 and the predetermined value set in the second compare register 11 is confirmed, the flip-flop 6 takes an inactivated state or the RESET state. Thus, the output signal TO on the output line 7 of the flip-flop 6 becomes a 0 state thereby the counting up of the time is completed.
The output signal on the output line 7 of the flip-flop 6 has the wave-form illustrated in FIG. 2. As described the above, a predetermined value T1 about the event count is set in the first compare register 10 prior to the initiation of the counting up operation by the first timer 1. The counting up operation of the event occurrences is continued until the correspondence between the present count value of the first timer 1 and the predetermined value T1 set in the first compare register 10 appears. In the meantime, the flip-flop 6 remains the RESET state and thus the output signal TO on the output line 7 of the flip-flop 6 remains the 0 state. The occurrence of the correspondence between the present count up value of the first timer 1 and the predetermined value T1 set in the first compare register 10 makes the flip-flop 6 activated. Thus, the flip-flop 6 takes the SET state thereby resulting in a 1 state of the output signal TO of the flip-flop 6. The second timer 13 initiates the count up operation of the time. The counting up operation of the time by the second timer 12 is continued until the present count value of the second timer 13 reaches a predetermined value T1+T2. In the meantime, the flip-flop 6 remains as the SET state. When the correspondence between the present count value of the time and the predetermined value T1+T2 is confirmed, the flip-flop 6 becomes the inactivated state or the RESET state. The output signal TO of the flip-flop 6 becomes the 0 state.
That is why the time count and the event count are conducted in a single pulse generating operation. In the above system, the external event base count, for example, T1 defines the delay in the pulse signal from the external reference signal INTP which makes the timer initiate the count operation and the time base count, for example, T2 defines the width of the pulse. Contrary to the above, it is of course available that the time base count defines the delay in pulse signal from the external reference signal INTP and the event base represents the width of the pulse.
As described the above, the conventional configuration of the pulse generating circuit requires at least two timers, and thus one is for the time count and other is for the event count. The use of the two timers in each of the pulse generating circuit is disadvantageous in view of the hardware. Such disadvantages are considerable when a large number of the pulse generating signals are used for the microcomputers. It is desirable to provide a novel circuit configuration which will allow the time base count and the event base count to be realized in a pulse generating operation by use of a single timer only.